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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 0 1 publication order number: NCV7383/d NCV7383 flexray bus driver NCV7383 is a single ? channel flexray bus driver compliant with the flexray electrical physical layer specification rev. 3.0.1, capable of communicating at speeds of up to 10 mbit/s. it provides differential transmit and receive capability between a wired flexray communication medium on one side and a protocol controller and a host on the other side. NCV7383 mode control functionality is optimized for nodes without the need of extended power management provided by transceivers with permanent connection to the car battery as is on ncv7381. NCV7383 is primarily intended for nodes switched off by ignition. it offers excellent electromagnetic compatibility (emc) and electrostatic discharge (esd) performance. key features general ? compliant with flexray electrical physical layer specification rev 3.0.1 ? flexray transmitter and receiver in normal ? power modes for communication up to 10 mbit/s ? support of 60 ns bit time ? flexray low ? power mode receiver for remote wakeup detection ? excellent electromagnetic susceptibility (ems) level over full frequency range. very low electromagnetic emissions (eme) ? bus pins protected against >10 kv system esd pulses ? safe behavior under missing supply or no supply conditions ? interface pins for a protocol controller and a host (txd, rxd, txen, stbn, bge, errn, csn, sck, sdo) ? supply pins v cc , v io with independent voltage ramp up: ? v cc supply parametrical range from 4.75 v to 5.25 v ? v io supply parametrical range from 2.3 v to 5.25 v ? txen timeout and bge feedback ? two error indication modes ? track mode ? error signaling on errn pin ? latched mode ? status register accessible via spi ? compatible with 14 v and 28 v systems ? operating ambient temperature ? 40 c to +125 c (t amb_class1 ) ? junction temperature monitoring ? tssop ? 14 package ? these are pb ? free devices flexray functional classes ? bus driver ? bus guardian interface ? bus driver logic level adaptation ? bus driver remote wakeup quality ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable marking diagram http://onsemi.com a = assembly location l = wafer lot y = year w = work week = pb ? free package 1 14 tssop ? 14 case 948g nv73 83 ? 0 alyw 1 14 see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. ordering information pin connections v io txd txen rxd bge stbn sck v cc bp bm gnd errn csn sdo 1 (top view)
NCV7383 http://onsemi.com 2 block diagram txd txen bge stbn rxd sdo gnd bp bm control logic transmitter normal mode/ low ? power mode receiver NCV7383 errn sck csn bus error detection wakeup detection voltage monitoring thermal shutdown host module bge module cc module spi module figure 1. block diagram v cc v io table 1. pin description pin number pin name pin type pin function 1 v io supply supply voltage for digital pins level adaptation 2 txd digital input, internal pd data to be transmitted 3 txen digital input, internal pu transmitter enable input; when high, transmitter disabled 4 rxd digital output receive data output 5 bge digital input, internal pd bus guardian enable input; when low, transmitter disabled 6 stbn digital input, internal pd mode control input 7 sck digital input, internal pu spi clock input 8 sdo digital output spi data output 9 csn digital input, internal pu or pd chip select input, active low 10 errn digital output bus driver error condition indication 11 gnd ground ground connection 12 bm high ? voltage analog input/output bus line minus 13 bp high ? voltage analog input/output bus line plus 14 v cc supply bus driver core supply voltage; 5v nominal notes: pu means pull ? up pd means pull ? down
NCV7383 http://onsemi.com 3 application information vbat bp bm gnd mcu + cc + bg vcc reg. vio reg. cmc out out in in NCV7383 bp bm gnd errn csn 1 2 3 4 txd 5 txen 6 rxd 7 bge 8 stbn 14 13 12 11 10 9 sdo sck host bus guardian flexray communication controller spi ecu figure 2. application diagram v cc v io c vio c vcc c bus r bus1 r bus2 table 2. recommended external components for the application diagram component function min typ max unit note c vcc decoupling capacitor on v cc supply line, ceramic 100 nf c vio decoupling capacitor on v io supply line, ceramic 100 nf r bus1 bus termination resistor 47.5 (note 1) r bus2 bus termination resistor 47.5 (note 1) c bus common ? mode stabilizing capacitor, ceramic 4.7 nf (note 2) cmc common ? mode choke 100 h 1. tolerance 1%, type 0805. the value r bus1 +r bus2 should match the nominal cable impedance. 2. tolerance 20%, type 0805
NCV7383 http://onsemi.com 4 functional description operating modes NCV7383 can switch between two operating modes depicted in figure 3. in normal mode, the chip interconnects a flexray communication controller with the bus medium for full ? speed communication. this mode is also referred to as normal ? power mode. in standby mode, the communication is suspended and the power consumption is substantially reduced. a wakeup on the bus can be detected and signaled to the host. the standby mode is referred to as low ? power mode. the operating mode selected is a function of the host signal stbn, the state of the supply voltages and the wakeup detection. as long as both supplies (v cc and v io ) remain above their respective under ? voltage detection levels, the logical control by stbn pin shown in figure 3 applies. influence of the power ? supplies and of the wakeup detection on the operating modes is described in subsequent paragraphs. normal mode transmitter: on receiver: on rxd: bus state spi: ready power cons.: normal standby mode transmitter: off receiver: wakeup ? detection rxd: wakeup flag spi: ready power cons.: low recovery from all uvs (stbn = h) unsupplied power cons.: low figure 3. state diagram stbn = l v cc or v iouv detected uv cc < uv cc_porl uv cc > uv cc_porh stbn = h (no uv) or stbn errn error flag wake flag normal mode error flag standby mode normal mode dbdmodechange dbdmodechange figure 4. timing diagram of operating modes control by the stbn pin power supplies and power supply monitoring NCV7383 is supplied by two pins. v cc is the main 5 v supply powering NCV7383 and the flexray bus driver core. v io supply serves to adapt the logical levels of NCV7383 to the host and/or the flexray communication controller digital signal levels. both supplies should be properly decoupled by filtering capacitors ? see figure 2 and t able 2. v io supply voltage can be applied prior to v cc during power ? up event, however the NCV7383 is not considered
NCV7383 http://onsemi.com 5 supplied until v cc supply voltage is above uv cc_porh threshold (v cc > uv cc_porh ) ? see table 3. both supplies are monitored by under ? voltage detectors with individual thresholds and filtering times both for under ? voltage detection and recovery ? see table 15. junction temperature monitoring in order to protect the NCV7383 from being damaged in case of thermal event, a junction temperature monitoring is implemented. high ambient temperature together with the device high power dissipation can lead to junction temperature reaching a critical temperature. under certain failure conditions (e.g. bus pin shorted to the supply voltage during the transmitter active state), the device power dissipation can be rapidly increased even though the absolute short current is limited. if the junction temperature is higher than t jsd (typically 165 c) in normal mode, thermal shutdown flag is set and the transmitter is disabled. this will reduce the power dissipation and decrease the junction temperature. the transmitter is enabled as soon as the thermal shutdown flag is cleared. this requires the junction temperature f alling below the thermal shutdown level and txen pin being set to high in normal mode. logic level adaptation level shift input v io is used to apply a reference voltage uv dig = uv io to all digital inputs and outputs in order to adapt the logical levels of NCV7383 to the host and/or the flexray communication controller digital signal levels. internal flags the NCV7383 control logic uses a number of internal flags (i.e. one ? bit memories) reflecting important conditions or events. table 3 summarizes the individual flags and the conditions that lead to a set or reset of the flags. table 3. internal flags flag set condition reset condition comment remote wakeup v cc under ? voltage flag is not set and remote wakeup is detected in standby mode normal mode is entered rxd and errn are set low if remote wakeup flag is set and stbn is low mode normal mode is entered normal mode is left transmitter ready all of the following terms are valid: the bus driver is in normal mode txen timeout flag is not set bge is high thermal shutdown flag is not set any of the following terms is valid: the bus driver is not in normal mode txen timeout flag is set bge is low thermal shutdown flag is set power ? on v cc power supply level becomes sufficient for the operation of the control logic normal mode is entered bus error transmitter is enabled and data on bus are different from txd signal (sampled after each txd edge) (transmitter is enabled and data on bus are identical to txd signal) or txen is set high or normal mode is left the bus error flag has no influence on the bus driver function thermal shutdown junction temperature is higher than tjsd (typ. 165 c) in a normal mode junction temperature is below tjsd in a normal mode and txen is high or normal mode is left the transmitter is disabled as long as the thermal shutdown flag is set txen time- out txen is low for longer than dbdtxact- ivemax (typ. 1.5 ms) in a normal mode txen is high or normal mode is left the transmitter is disabled as long as the timeout flag is set v cc under ? volt- age v cc is below the under ? voltage threshold for longer than dbduvv cc v cc is above the under ? voltage thresh- old for longer than dbdrv cc standby mode is forced as long as the v cc uv flag is set v io under ? volt- age v io is below the under ? voltage threshold for longer than duv io v io is above the under ? voltage thresh- old for longer than dbdrv io or remote wakeup flag becomes set standby mode is forced as long as the v io uv flag is set
NCV7383 http://onsemi.com 6 table 3. internal flags flag comment reset condition set condition spi error spi error is detected: number of sck falling edges while csn is low is different from 16 or sck is not low at csn falling or rising edge csn falling edge is detected or track mode is entered the status bits update is discarded if spi error is detected error any of the following flags is set: ? bus error ? thermal shutdown ? txen timeout ? v cc under ? voltage ? v io under ? voltage ? spi error all of the following flags (track mode) or status bits (latched mode) are reset: ? bus error ? thermal shutdown ? txen timeout ? v cc under ? voltage ? v io under ? voltage ? spi error errn is set low if error flag is set and stbn is high internal error flag there are two error signaling modes: ? track mode ? the common error flag is reset when all of the error related flags are reset ? error flag is directly visible on errn pin if stbn pin is high. minimum errn pin indication time is dbderrn stable . ? latched mode ? the common error flag is reset when all of the related status bits are reset (requires successful status register read ? out while all these flags are reset). the common error flag is visible on errn pin if stbn pin is high and the particular flags are accessible via spi interface. after power ? up the error signaling is switched to the latched mode by default (internal pull ? up on csn pin). when v io is not in under ? voltage error indication track mode can be selected by host request (setting csn pin low for longer than derrnmodechange while sck is set high ? see figure 5), or simply by leaving csn pin permanently connected to gnd and sck pin permanently connected to v io . as soon as error indication track mode is selected, csn pin internal pull ? up is switched to pull ? down providing the csn pin input current is reduced. csn sck error indication latched mode error indication track mode derrnmodechange (internal pull ? up) error indication latched mode (internal pull ? up) (internal pull ? down) (internal pull ? up) don?t care don?t care figure 5. timing diagram of error indication mode control.
NCV7383 http://onsemi.com 7 errn pin signaling provided v io supply is present together with v cc , the digital output errn indicates the state of the internal ?error? flag when the normal mode is commanded by stbn and the state of the internal ?wake? flag when the standby mode is commanded by stbn. the polarity of the indication is reversed ? errn pin is pulled low when the ?error? flag or ?wake? flag (depends on stbn pin state) is set. the signaling on pin errn is functional in both operating modes. table 4. signaling on errn pin stbn description error flag wake flag errn high detected error signaling not set x high set x low low detected wakeup event signaling x not set high x set low failure conditions handling safe behavior of the NCV7383 is guaranteed in order not to disturb the rest of the flexray network in case the NCV7383 is under following fault conditions: ? undervoltage on v io and/or v cc ? standby mode is entered and transmitter is disabled ? bp or bm is shorted to gnd or to supply voltage ? the absolute bus pins output current is limited ? bp and bm are shorted together ? the absolute bus pins output current is limited ? gnd pin is unconnected while all digital inputs are high ? absolute bp and bm leakage current and input current of the digital input pins are limited. ? txen is low for longer than dbdtxactivemax (typ. 1.5 ms) when the NCV7383 is in a normal mode ? the transmitter is disabled ? junction temperature exceeds the thermal shutdown temperature (t jsd , typ. 165 c) when the NCV7383 is in a normal mode ? the transmitter is disabled spi interface and status register a full set of internal bits referred to as status register can be read through the serial peripheral interface (spi). the status register content is described in table 5 while an example of the read ? out waveform is shown in figure 6. as long as the csn chip select is high, the sck clock input is not relevant and the sdo output is kept in high ? impedance state. the signal on the sck input is taken into account only when csn chip select input is set to low. the individual status bits are channeled to sdo pin at the rising edge on sck pin. the NCV7383 spi supports baud rates from 10 kbit/s to 2 mbit/s. the status register consist of 16 main bits and 16 additional bits providing information about the analog and digital part version. the read ? out always starts with bit s0. one spi frame consists of exactly sixteen bits transferred from the NCV7383 to the host through output pin sdo. the number of sck falling edges is checked on every spi frame. if the number is different from 16, the spi frame is considered as incorrect, spi frame error flag is set and the status register bits s4 ? s10 are not reset when the read ? out is finished. as soon as the csn is set to high and no violation was detected in the spi frame, the read ? out is considered as finished. at the same time, the status register bits s4 to s10 are reset provided the corresponding flags are reset ? see table 5. additionally, the total number of bits shifted to sdo during the read ? out can be extended to 32, considering the spi frame incorrect. this provides ability to obtain the additional status register bits identifying the production masks version. such spi frame sets the spi frame error flag and the status register bits s4 ? s10 are not reset when the read ? out is finished. spi interface is fully functional only if latched error indication mode is selected and v io supply is not in undervoltage. spi interface is disabled in power ? off mode (v cc < uv cc_porl ) even if v io supply voltage is not in undervoltage.
NCV7383 http://onsemi.com 8 csn sck sdo s0 s14 s15 figure 6. definition of spi timing parameters t csn_sck t sck_per t sck_high t sck_low t sck_sdo t csn_sdo t csn_sdo t sck_csn t csn_high table 5. status register bit number status bit content note reset after finished read ? out s0 remote wakeup flag reflects directly the corresponding flag no s1 mode flag s2 transmitter ready flag s3 bge feedback normal mode: bge pin logical state (note 3) other modes: low ? s4 power ? on status the status bit is set if the corresponding flag was set previously (the respective high level of the flag is latched in its sta- tus counter ? part) yes, if the corresponding flag is re- set and the spi frame was correct (no spi error) s5 bus error status s6 thermal shutdown status s7 txen timeout status s8 v cc under ? voltage status s9 v io under ? voltage status s10 spi error status s11 not used; always low ? ? s12 not used; always high ? ? s13 not used; always low ? ? s14 not used; always high ? ? s15 parity exclusive ? or of status bits s0 ? s14 ? s16 ? s23 version of the NCV7383 analog part fixed values identifying the production masks version. cannot be read out with- out detection of an spi error ? s24 ? s31 version of the NCV7383 digital part 3. the bge pin state is latched during status bit s2 read ? out, at the sck pin falling edge.
NCV7383 http://onsemi.com 9 mode changes caused by internal flags changes of some internal flags described in table 3 can force an operating mode transition complementing or overruling the operating mode control by the digital input stbn which is shown in figure 3: ? setting the v io or v cc under ? voltage flag causes a transition to the standby mode ? reset of the under ? voltage flag (i.e. recovery from under ? voltage) re ? enables the control of the chip by digital input stbn. ? setting of the wake flag causes the reset of all under ? voltage flags. the NCV7383 stays in the standby mode. flexray bus driver NCV7383 contains a fully ? featured flexray bus driver compliant with electrical physical layer specification rev. 3.0.1. the transmitter part translates logical signals on digital inputs txen, bge and txd into appropriate bus levels on pins bp and bm. a transmission cannot be started with data_1. in case the txen is set low for longer than dbdtxactivemax in normal mode, the txen timeout flag is set and the transmitter is disabled. the receiver part monitors bus pins bp and bm and signals the detected levels on digital output rxd. the different bus levels are defined in figure 7. the function of the bus driver and the related digital pins in different operating modes is detailed in tables 6 and 7. ? the transmitter can only be enabled if the activation of the transmitter is initiated in normal mode. ? the normal mode receiver function is enabled by entering the normal mode. ? the low power receiver function is enabled by entering the standby mode. ubus bp bm idle_lp idle data_0 data_1 figure 7. flexray bus signals v cc /2 table 6. transmitter function and transmitter ? related pins operating mode bge txen txd transmitted bus signal standby x x x idle_lp normal 0 x x idle 1 1 x idle 1 0 0 data_0 1 0 1 data_1 table 7. receiver function and receiver ? related pins operating mode signal on bus wake flag rxd standby x not set high x set low normal idle x high data_0 x low data_1 x high bus guardian interface the interface consists of the bge digital input signal allowing a bus guardian unit to disable the transmitter. bus driver remote wakeup detection during the standby mode and under the presence of v cc voltage, a low ? power receiver constantly monitors the
NCV7383 http://onsemi.com 10 activity on bus pins bp and bm. a valid remote wake ? up is detected when either a wakeup pattern or a dedicated wakeup frame is received. a wakeup pattern is composed of two data_0 symbols separated by data_1 or idle symbols. the basic wakeup pattern composed of data_0 and idle symbols is shown in figure 8; the wakeup pattern composed of data_0 and data_1 symbols ? referred to as ?alternative wakeup pattern? ? is depicted in figure 9. a remote wake ? up is detected even if a transition from normal mode to standby mode takes place while a valid wakeup pattern is being received (if the wakeup pattern starts in normal mode and ends in standby mode). udata0_lp ubus idle(_lp) data_0 idle(_lp) data_0 idle(_lp) 0 remote wakeup detected figure 8. valid remote wakeup pattern >dwu 0detect >dwu idledetect >dwu 0detect >dwu idledetect dwu 0detect >dwu idledetect >dwu 0detect >dwu idledetect NCV7383 receives a full flexray frame at 10 mbit/s with the following payload data: 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff the wakeup pattern, the alternative wakeup pattern and the wakeup frame lead to identical wakeup treatment and signaling.
NCV7383 http://onsemi.com 11 absolute maximum ratings table 8. absolute maximum ratings symbol parameter min max unit uv cc ? max 5v supply voltage ? 0.3 5.5 v uv io ? max supply voltage for v io voltage level adaptation ? 0.3 5.5 v udigin max dc voltage at digital inputs (stbn, txd, txen, bge, scsn, sclk) ? 0.3 5.5 v udigout max dc voltage at digital outputs (rxd, errn, sdo) ? 0.3 v io +0.3 v idigout in ? max digital output pins input current (v io = 0 v) ? 10 10 ma ubm max dc voltage at pin bm ? 50 50 v ubp max dc voltage at pin bp ? 50 50 v t j_max junction temperature ? 40 175 c t stg storage temperature range ? 55 150 c uesd iec system hbm on pins bp and bm (as per iec 61000 ? 4 ? 2; 150 pf/330 ) ? 10 +10 kv uesd ext component hbm on pins bp, bm (as per eia ? jesd22 ? a114 ? b; 100 pf/1500 ) ? 8 +8 kv uesd int component hbm on all other pins (as per eia ? jesd22 ? a114 ? b; 100 pf/1500 ) ? 4 +4 kv uv tran voltage transients, pins bp and bm according to iso7637 ? 2, class c (note 4) test pulses 1 ? 100 ? v test pulses 2a ? +75 v test pulses 3a ? 150 ? v test pulses 3b ? +100 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. test is carried out according to setup in flexray physical layer emc measurement specification, version 3.0 . this specification is referring to iso7637. test for higher voltages is planned. operating ranges table 9. NCV7383: operating ranges symbol parameter min max unit uv cc ? op supply voltage 5 v 4.75 5.25 v uv io ? op supply voltage for v io voltage level adaptation 2.3 5.25 v udigio op dc voltage at digital pins (txd, txen, rxd, bge, stbn, errn, scsn, sclk, sdo) 0 v io v ubm op dc voltage at pin bm ? 50 50 v ubp op dc voltage at pin bp ? 50 50 v t amb ambient temperature (note 5) ? 40 125 c t j_op junction temperature ? 40 150 c 5. the specified range corresponds to t amb_class1
NCV7383 http://onsemi.com 12 thermal characteristics table 10. package thermal resistance symbol rating value unit r ja_1 thermal resistance junction ? to ? air, jedec 1s0p pcb 153 k/w r ja_2 thermal resistance junction ? to ? air, jedec 2s2p pcb 104 k/w electrical characteristics the characteristics defined in this section are guaranteed within the operating ranges listed in table 9, unless stated otherwi se. positive currents flow into the respective pin. table 11. current consumption symbol parameter conditions min typ max unit iv cc ? norm ? idle current consumption from v cc normal mode ? bus signals idle 15 ma iv cc ? norm ? active normal mode ? bus signals data_0/1 r bus = no load 37 ma normal mode ? bus signals data_0/1 r bus = 40 ? 55 72 ma iv cc ? lp standby mode, t j 85 c (note 6) 30 a iv io ? norm current consumption from v io normal mode 1 ma iv io ? lp standby mode, t j 85 c (note 6) 6 a itot ? lp total current consumption ? sum from all supply pins standby mode 53 a standby mode, t j < 85 c (note 6) 37 a standby mode, t j < 25 c (note 6) 24 a 6. values based on design and characterization, not tested in production table 12. transmission parameters symbol parameter conditions min typ max unit ubdtx active differential voltage |ubp ? ubm| when sending symbol ?data_0? or ?data_1? (functional class bus driver increased voltage amplitude transmitter) r bus = 40 ? 55 ; c bus = 100 pf parameters defined in figure 10. 600 2000 mv ubdtx idle differential voltage |ubp ? ubm| when driving signal ?idle? 0 25 mv dbdtx10 transmitter delay, negative edge test setup as per figure 14 with r bus = 40 ; c bus =100 pf sum of txd signal rise and fall time (20% ? 80% v io ) of up to 9 ns parameters defined in figure 10. 60 ns dbdtx01 transmitter delay, positive edge 60 ns dbdtxasym transmitter delay mismatch, |dbdtx10 ? dbdtx01| (note 8) 4 ns dbustx10 fall time of the differential bus voltage from 80% to 20% 6 18.75 ns dbustx01 rise time of the differential bus voltage from 20% to 80% 6 18.75 ns dbustxdif differential bus voltage fall and rise time mismatch |dbustx10 ? dbustx01| 3 ns 7. values based on design and characterization, not tested in production 8. guaranteed for 300mv and 150 mv level of ubus 9. not tested in production. limits based on bus driver simulations. for more information see flexray communication system ? electrical physical layer specification, version 3.0.1 .
NCV7383 http://onsemi.com 13 table 12. transmission parameters symbol unit max typ min conditions parameter dtxen low time span of bus activity test setup as per figure 14 with r bus = 40 ; c bus = 100 pf parameters defined in figure 11. 550 650 ns dbdtxia transmitter delay idle ? > active 75 ns dbdtxai transmitter delay active ? > idle 75 ns dbdtxdm idle ? active transmitter delay mismatch | dbdtxia ? dbdtxai | 50 ns dbustxia transition time idle >active 30 ns dbustxai transition time active > idle 30 ns dbdbgeia bge delay idle ? > active (note 7) r bus = 40 ; c bus = 100 pf 75 ns dbdbgeai bge delay active > idle (note 7) 75 ns dbdtxactivemax maximum length of transmitter activation 650 2600 s ibp bmshortmax ibm bpshortmax absolute maximum output current when bp shorted to bm ? no time limit r shortcircuit 1 60 ma ibp gndshortmax ibm gndshortmax absolute maximum output current when shorted to gnd ? no time limit r shortcircuit 1 60 ma ibp ? 5vshortmax ibm ? 5vshortmax absolute maximum output current when shorted to ? 5 v ? no time limit r shortcircuit 1 60 ma ibp bat27shortmax ibm bat27shortmax absolute maximum output current when shorted to 27 v ? no time limit r shortcircuit 1 60 ma ibp bat48shortmax ibm bat48shortmax absolute maximum output current when shorted to 48 v ? no time limit r shortcircuit 1 72 ma r bdtransmitter bus interface equivalent output impedance bus driver simulation model parameter (note 9) 31 105 500 7. values based on design and characterization, not tested in production 8. guaranteed for 300mv and 150 mv level of ubus 9. not tested in production. limits based on bus driver simulations. for more information see flexray communication system ? electrical physical layer specification, version 3.0.1 .
NCV7383 http://onsemi.com 14 dbdtx10 dbdtx01 dbustx10 dbustx01 100% 80% 20% 0% utxd 300 mv ? 300 mv ubus 100...4400ns txd signal is constant for 100..4400 ns before the first edge. all parameters values are valid even if the test is performed with opposite polarity. figure 10. transmission parameters (txen is low and bge is high) ubdtx active ? ubdtx active 100% v io 50% v io 0% v io dbdtxia dbdtxai dbustxia dbustxai utxen ? ubdtx ? 30 mv ? 300 mv ubus figure 11. transmission parameters for transitions between idle and active (txd is low) 100% v io 50% v io 0% v io dtxen low
NCV7383 http://onsemi.com 15 table 13. reception parameters symbol parameter conditions min typ max unit udata0 receiver threshold for detecting data_0 activity detected previously. |ubp ? ubm| 3 v ? 300 ? 150 mv udata1 receiver threshold for detecting data_1 150 300 mv |udata1| ? |udata0| mismatch of receiver thresholds (ubp+ubm)/2 = 2.5 v ? 30 30 mv udata0_lp low power receiver threshold for detecting data_0 uv cc = 5 v. ? 400 ? 100 mv ucm common mode voltage range (with respect to gnd) that does not disturb the receiver function and reception level parameters ubp = (ubp+ubm)/2 (note10) ? 10 15 v ubias bus bias voltage during bus state idle in normal mode r bus = 40 ? 55 ; c bus = 100 pf (note 11) 1800 2500 3150 mv bus bias voltage during bus state idle in standby mode ? 100 0 100 mv r cm1 , r cm2 receiver common mode resistance (note 11) 10 40 k c_bp, c_bm input capacitance on bp and bm pin (note 13) f = 5 mhz 20 pf c_bus dif bus differential input capacitance (note 13) f = 5 mhz 5 pf ibp leak ibm leak absolute leakage current when driver is off ubp = ubm = 5 v all other pins = 0 v 5 a ibp leakgnd ibm leakgnd absolute leakage current, in case of loss of gnd ubp = ubm = 0 v all other pins = 16 v 1600 a ubusrx data test signal parameters for reception of data_0 and data_1 symbols test signal and parameters defined in figures 12 and 13. rxd pin loaded with 25 pf capacitor. 400 3000 mv dbusrx0 bd 60 4330 ns dbusrx1 bd 60 4330 ns dbusrx10 22.5 ns dbusrx01 22.5 ns dbdrx10 receiver delay, negative edge (note 12) 75 ns dbdrx01 receiver delay, positive edge (note 12) 75 ns dbdrxasym receiver delay mismatch |dbdrx10 ? dbdrx01| (note 12) 5 ns ubusrx test signal parameters for bus activity detection 400 3000 mv dbusactive 590 610 ns dbusidle 590 610 ns dbusrxia 18 22 ns dbusrxai 18 22 ns dbdidledetection bus driver filter ? time for idle detection 50 200 ns dbdactivitydetection bus driver filter ? time for activity detection 100 250 ns dbdrxai bus driver idle reaction time 100 275 ns dbdrxia bus driver activity reaction time 100 325 ns dbdtxrxai idle ? loop delay 300 ns 10. tested on a receiving bus driver. sending bus driver has a ground offset voltage in the range of [ ? 12.5 v to +12.5 v] and sends a 50/50 pattern. 11. bus driver is connected to gnd and uv cc = 5 v. 12. guaranteed for 300 mv and 150 mv level of ubus 13. values based on design and characterization, not tested in production
NCV7383 http://onsemi.com 16 dbdrx10 urxd 300 mv ? 300 mv ubus 150 mv ? 150 mv dbusrx10 dbusrx01 dbdrx01 figure 12. reception parameters 100% v io 50% v io 0% v io ? ubusrx data ubusrx data dbusrx0 bd dbusrx1 bd dbdrxia dbusactive urxd ? ubusrx ? 300 mv ubus ? 150 mv dbusrxia dbusidle dbdrxai ? 30 mv dbusrxai figure 13. parameters of bus activity detection 100% v io 50% v io 0% v io
NCV7383 http://onsemi.com 17 table 14. remote wake ? up detection parameters symbol parameter conditions min typ max unit dwu 0detect wake ? up detection time for data_0 symbol 1 4 s dwu idledetect wake ? up detection time for idle/data_1 1 4 s dwu timeout total wake ? up detection time (note 15) 50 140 s dwu interrupt acceptance timeout for interruptions (note 14) 0.13 1 s dbdwakeup reaction remote reaction time after remote wakeup event (note 15) 50 s 14. the minimum value is only guaranteed, when the phase that is interrupted was continuously present for at least 870ns. 15. values based on design and characterization, not tested in production table 15. power supply monitoring parameters symbol parameter conditions min typ max unit ubduvv cc v cc under ? voltage threshold 4 4.5 v uuv io v io under ? voltage threshold 2 2.3 v uuv_hyst hysteresis of the under ? voltage detectors 20 100 200 mv dbduvv cc v cc undervoltage detection time (note 16) 35 60 100 s dbduvv io v io undervoltage detection time (note 16) 35 60 100 s dbdrv cc v cc undervoltage recovery time (note 16) 35 60 100 s dbdrv io v io undervoltage recovery time (note 16) 14 30 48 s uv cc_porh v cc threshold for power on event 3.0 3.9 v uv cc_porl v cc threshold for power off event 2.95 3.85 v 16. values based on design and characterization, not tested in production table 16. temperature monitoring parameters symbol parameter conditions min typ max unit t jsd thermal shut ? down level 150 165 185 c table 17. host interface timing parameters symbol parameter conditions min typ max unit dbdmodechange stbn level filtering time for operating mode transition (note 17) 14 50 s dreactiontime errn reaction time on errn pin 50 s dbderrn stable error signaling time track mode 1 10 s derrnmodechange error signaling mode change request detection time latched mode v io uv flag not set 95 330 s 17. values based on design and characterization, not tested in production table 18. spi interface timing characteristics symbol parameter conditions min typ max unit dcsn_sck first spi clock edge after csn active 250 ns dsck_csn last spi clock edge before csn inactive 250 ns dcsn_sdo sdo output stable after csn active 150 ns sdo output high ? z after csn inactive 150 ns dsck_per spi clock period 0.5 100 s dsck_high duration of spi clock high level 250 ns dsck_low duration of spi clock low level 250 ns dsck_sdo sdo output stable after an spi clock rising edge 150 ns dcsn_high spi inter ? frame space (csn inactive) 250 ns
NCV7383 http://onsemi.com 18 digital input signals table 19. digital input signals voltage thresholds (pins stbn, bge, txen, csn, sck) symbol parameter conditions min typ max unit uv dig ? in ? low low level input voltage uv dig = uv io ? 0.3 0.3*v io v uv dig ? in ? high high level input voltage 0.7*v io 5.5 v table 20. txd pin parameters symbol parameter conditions min typ max unit ubdlogic_0 low level input voltage ? 0.3 0.4*v io v ubdlogic_1 high level input voltage 0.6*v io 5.5 v r pd _txd pull ? down resistance 5 11 20 k itxd il low level input current utxd = 0 v ? 1 0 1 ua c_bdtxd input capacitance on txd pin utxd = 100 mv, f = 5 mhz (note 18) 10 pf 18. values based on design and characterization, not tested in production table 21. txen pin parameters symbol parameter conditions min typ max unit r pu _txen pull ? up resistance 50 110 200 k itxen ih high level input current utxen = v io ? 1 0 1 a itxen leak input leakage current utxen = 5.25v, v io = 0 v ? 1 0 1 a table 22. stbn pin parameters symbol parameter conditions min typ max unit r pd _stbn pull ? down resistance 50 110 200 k istbn il low level input current ustbn = 0 v ? 1 0 1 a table 23. bge pin parameters symbol parameter conditions min typ max unit r pd _bge pull ? down resistance 150 500 k ibge il low level input current ubge = 0 v ? 1 0 1 a table 24. csn pin parameters symbol parameter conditions min typ max unit r pu _csn pull ? up resistance latched mode 50 110 200 k icsn ih high level input current latched mode, ucsn = v io ? 1 0 1 a r pd _csn pull ? down resistance track mode 50 110 200 k icsn il low level input current track mode, ucsn = 0v ? 1 0 1 a icsn leak input leakage current ucsn = 5.25v, v io = 0v ? 1 0 1 a table 25. sck pin parameters symbol parameter conditions min typ max unit r pu _sck pull ? up resistance 50 110 200 k isck ih high level input current, usck = v io ? 1 0 1 a isck leak input leakage current usck = 5.25v, v io = 0 v ? 1 0 1 a
NCV7383 http://onsemi.com 19 digital output signals table 26. digital output signals voltage limits (pins rxd, errn and sdo) symbol parameter conditions min typ max unit uv dig ? out ? low low level output voltage irxd ol = 3 ma, ierrn ol = 0.7 ma, isdo ol = 1 ma (note 19) 0 0.2*v io v uv dig ? out ? high high level output voltage irxd oh = ? 3 ma, ierrn oh = ? 0.7 ma, isdo oh = ? 1 ma (note 19) 0.8*v io v io v uv dig ? out ? uv output voltage on a digital output when v io in undervoltage (note 20) r load = 100 k to gnd, v cc supplied 500 mv uv dig ? out ? off output voltage on a digital output when unsupplied r load = 100 k to gnd 500 mv 19. uv dig = uv io . no undervoltage on v io and v cc supplied. 20. rxd and errn outputs forced low, sdo output switched to high impedance state table 27. rxd pin parameters symbol parameter conditions min typ max unit dbdrxd r15 rxd signal rise time (20% ? 80% v io ) rxd pin loaded with 15 pf capacitor (note 21) 6.5 ns dbdrxd f15 rxd signal fall time (20% ? 80% v io ) 6.5 ns dbdrxd r15 + dbdrxd f15 sum of rise and fall time (20% ? 80% v io ) 13 ns |dbdrxd r15 ? dbdrxd f15 | difference of rise and fall time 5 ns dbdrxd r25 rxd signal rise time (20% ? 80% v io ) rxd pin loaded with 25 pf capacitor 8.5 ns dbdrxd f25 rxd signal fall time (20% ? 80% v io ) 8.5 ns dbdrxd r25 + dbdrxd f25 sum of rise and fall time (20% ? 80% v io ) 16.5 ns |dbdrxd r25 ? dbdrxd f25 | difference of rise and fall time 5 ns dbdrxd r10_ms + dbdrxd f10_ms rxd signal sum of rise and fall time at tp4_cc (20% ? 80% v io ) rxd pin loaded with 10 pf at the end of a 50 , 1 ns microstripline (note 22) 16.5 ns |dbdrxd r10_ms ? dbdrxd f10_ms | rxd signal difference of rise and fall time at tp4_cc (20% ? 80% v io ) 5 ns 21. values based on design and characterization, not tested in production 22. simulation result. simulation performed within t j_op range, according to flexray electrical physical layer specification, version 3.0.1 figure 14. test setup for dynamic characteristics NCV7383 gnd bp bm rxd 25 pf 100 nf 100 nf c bus r bus 5 v dc v io v cc
NCV7383 http://onsemi.com 20 figure 15. test setup for transients test pulses NCV7383 gnd bp bm 56 330 pf 330 pf 100 nf iso 7637 ? 2 pulse generator rxd 15 pf 22 f 100 nf 22 f 5 v dc 3.3 v dc + v io v cc + r bus ordering information device description temperature range package shipping ? NCV7383db0r2g clamp 15 flexray transceiver ? 40 c to +125 c tssop ? 14 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV7383 http://onsemi.com 21 package dimensions tssop ? 14 case 948g issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCV7383/d flexray is a trademark of the flexray consortium. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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